DDR5 Electrical Challenges in High-Speed Server Design

Memory technologies are constantly trying to keep-up pace with the ever-increasing demand for compute and bandwidth. In high-speed servers, the single-ended technology of double data rate (DDR) synchronous dynamic random-access memory (SDRAM) has evolved from its humble beginnings to its fifth generation in DDR5. DDR5 operating speed can range from 3200 Mbps to north of 6400 Mbps (~ 8000 Mbps). In servers, DDR5 is usually supported through dual in-line memory modules (DIMMs). As the DDR speeds continue to increase, the operating margins are shrinking to tens of millivolts and picoseconds. Any imperfection in the channel routing can adversely impact the signal integrity (SI) margins.In this paper, SI challenges related to operating a single-ended DDR5 interface at such high-speeds is discussed. Various test cases are used to demonstrate the numerous challenges. The scenarios covered in this paper include the effects of channel imperfections like reflections and crosstalk, the importance of optimal routing layer assignment, impact of multiple DIMMs in the channel and the value of receiver equalization.