28 Gbaud PAM-4 Burst-Mode CDR With Reconfigurable Sampling Scheme

This paper presents a fast-locking 28 Gbaud PAM-4 CDR targeting for burst-mode operation. By implementing an oversampling scheme tailored for the preamble stage signal according to the pattern appearance regulation, the trade-off between the loop bandwidth and the convergence time in the conventional CDR is avoided. In addition, to reduce power consumption in the oversampling mode, a 3-phase sampling scheme equivalent to 3 times-oversampling with a minimal phase shift range of 30° is proposed. The PAM-4 burst-mode CDR also includes a conventional Bang-Bang phase locking loop with a bandwidth of 5 MHz. Realized in a 65nm bulk CMOS technology, the CDR chip achieves 28 Gbaud PAM-4 burst-mode clock recovery within 10 ns. With integrating slicers, phase interpolators and output buffers, the total power consumption of the CDR is 154 mW. Compared with the prior arts, to the best of authors' knowledge, the proposed CDR first achieves on-chip phase-locking with PAM-4 Burst signals, based on the proposed PAM-4 burst-mode signal tailored 3-phase oversampling scheme.