An 8–11b 320kS/s resolution scalable noise shaping SAR ADC

This work presents an 8 - 11b resolution scalable and energy efficient ADC, using the oversampled and noise shaping SAR architecture in 90nm UMC CMOS process. Further, the proposed ADC simplifies the design of the noise shaping filter to enable the use of a first order switched capacitor low pass filter for shaping the comparator noise and the in band quantization noise. The ADC design alleviates the matching concerns by using only an 8b capacitive DAC, and allows to configure the ADC architecture from an 8b traditional SAR ADC up to an 11b ADC by enabling the oversampling and noise shaping loops within the SAR architecture. This ADC is designed to operate with 8-11b resolution, up to 320kS/s, achieving a power scaling from 80nW to 1.5μW, resulting in an average FoM of 30fJ/conv-step.