A 7.9-ENOB 1. 5GS/s Common-Mode and Temperature Insensitive Pipelined-SAR ADC with an On-Chip Temperature-Sensor-Based Stage-Gain Compensation

Pipelined-SAR ADCs utilizing a dynamic amplifier (DA) as a residue amplifier (RA) has become popular due to its potential to achieve both high speed and excellent power efficiency. A notable challenge though is that the gain of the DA is sensitive to process and temperature as well as to input common-mode voltage ($\mathrm{V}_{\mathrm{l}\mathrm{N}\mathrm{C}\mathrm{M}}$). Although there are several previous works aiming at compensating the temperature sensitivity of the DA [1], the lack of regulating DA’s output common-mode voltage (VOUTCM) makes them hard to be applied to pipelined ADCs having more than two stages. This is because the variation of VOUTCM directly leads to $\mathrm{V}_{\mathrm{l}\mathrm{N}\mathrm{C}\mathrm{M}}$ variation of the DA in the subsequent stage, significantly impacting the gain of the DA. Also, due to DA’s high |$\Delta \mathrm{v}_{0\cup \mathrm{T}\mathrm{C}\mathrm{M}/\Delta \mathrm{V}_{\mathrm{l}\mathrm{N}\mathrm{C}\mathrm{M}}|}$, small $\mathrm{V}_{\mathrm{l}\mathrm{N}\mathrm{C}\mathrm{M}}$ variation at the ADC input propagates through the stages, potentially driving the DA in the later stages out of acceptable $\mathrm{V}_{\mathrm{l}\mathrm{N}\mathrm{C}\mathrm{M}}$ range. This work presents a promising solution to such challenges with a new reset scheme and an on-chip temperature-sensor-based gain compensation scheme for the DA. The measured results validate that the ADC with proposed techniques operates reliably over temperature variation of 100°C and $\mathrm{V}_{\mathrm{l}\mathrm{N}\mathrm{C}\mathrm{M}}$ variation of 112mV.