Relaxation Digital-to-Analog Converters Featuring Self-Calibration and Parasitics-Induced Error Suppression in 180 nm CMOS

The design and the silicon characterization of two mostly digital, low-voltage, energy- and area-efficient Relaxation Digital-to-Analog Converters (ReDACs) in 180 nm featuring digital self-calibration and parasitics-induced error suppression are presented and compared in this paper. The first design is a single-ended ReDAC (SE-ReDAC) and operates at 880 kS/s with a 10-bit resolution, while the second is based on a differential ReDAC (Diff-ReDAC) architecture and operates at 100 kS/s with a 13-bit resolution. The SE-ReDAC testchip in 180nm occupies just 5,030 μm ² and operates with a supply voltage ranging from 0.6V to 1V. Experimental results at 0.65V reveal a 72.18 dB-SFDR, a 65.59 dB-THD and a 56.09 dB SINAD, resulting in 9.02 ENOB, with a power dissipation of just 3.3μW, achieving a competitive energy-efficiency (area-normalized energy efficiency) figure of merit FOM (FOM _A ) of 166 dB (175 dB). On the other hand, the 180-nm Diff-ReDAC testchip occupies 7,800 μm ² and operates in a supply voltage range from 0.45V to 1V, while achieving a 77.81 dB-SFDR, a 77.52 dB-THD and a 65.82 dB-SINAD (10.64 ENOB) at 0.6V supply with a power consumption of just 880nW, leading to a very competitive FOM (FOM _A ) of 172 dB (178 dB).