Vertically stacked van der Waals heterostructures for three-dimensional circuitry elements

Abstract Two-dimensional (2D) layered materials have been actively explored for electronic device applications because of their ability to form van der Waals heterostructures with unique electronic properties. Vertical integration of atomically thin 2D materials can enable the design of a three-dimensional (3D) circuit which is a promising pathway to continuously increase device density. In this study, we vertically stack 2D materials, such as graphene (Gr), MoS 2 , and black phosphorus (BP) to build transistors, heterostructure p–n diodes, and 3D logic circuits. The vertical transistors built from MoS 2 or BP semiconductor exhibit a good on-off ratio of up to 10 3 and a high current density of ∼200 Acm −2 at a very small V DS of 50 mV. The Gr/BP/MoS 2 vertical heterostructure p–n diodes show a high gate-tunable rectification ratio of 10 2 . Finally, we have demonstrated a 3D CMOS inverter by vertical integration of Gr, BP (p-channel), Gr, MoS 2 (n-channel), and a 50-nm-thick gold film in sequence. The ability to vertically stack 2D layered materials by van der Waals interactions offers an alternative way to design future 3D integrated circuits.