原子层沉积
材料科学
电介质
电迁移
沟槽
接触电阻
图层(电子)
沉积(地质)
堆栈(抽象数据类型)
氧化物
光电子学
抵抗
硅
纳米技术
复合材料
冶金
计算机科学
古生物学
沉积物
生物
程序设计语言
作者
Marleen H. van der Veen,Jan Willem Maes,O. Varela Pedreira,Chiyu Zhu,Davide Tierno,Sukanya Datta,N. Jourdan,Stefan Decoster,Chen Wu,Moataz Mousa,Youngchul Byun,Herbert Struyf,S. Park,Zsolt Tökei
标识
DOI:10.1109/iitc/mam57687.2023.10154783
摘要
Selective atomic layer deposition (ALD) of Mo is explored to fill 10nm contacts in a 2 nm node test vehicle. The ALD Mo deposition is highly selective towards the dielectrics (SiO 2 , low-k OSG3.0, SiCN), and deposits selectively on the bottom Ru routing contact layer. Barrierless Mo via fill levels in the range of 10-20nm are obtained without detecting Mo in the dielectrics of the stack. The resistance of the Mo in MP24 vias with aspect ratio (AR) 2 is ~ 50Ω. Further resistance reduction is expected upon removing the top interfacial oxide introduced by an air break during metallization. The reliability shows that stress induced voiding is not observed for the Mo-Cu metallized system. Additionally, the via electromigration failures are only observed in the connecting Cu top trench, leaving the robust ALD Mo vias intact.
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