Wafer-scale graphene electro-absorption modulators fabricated in a 300 mm CMOS platform

Graphene-based devices have garnered significant attention for their potential in numerous applications, notably in integrated photonics. For graphene devices to be used in real-world systems, it is necessary to demonstrate competitive device performance, repeatability of results, reliability, and a path to large-scale manufacturing with high yield at low cost. In this study, single-layer graphene electro-absorption modulators serve as a pivotal test vehicle to facilitate wafer-scale integration in a 300mm pilot CMOS foundry, harnessing imec silicon photonics platforms along with the 6- inch graphene transfer capabilities of Graphenea. The patterning of graphene is achieved utilizing a hardmask, with tungsten-based contacts being developed via the damascene method to facilitate CMOS-compatible manufacturing. Through an extensive analysis of inline metrology data during process development along with analysis of hundreds of devices on each wafer, the impact of specific processing steps on the performance could be identified and optimized. Subsequent to optimization, a modulation depth of 50 ± 4 dB/mm is exemplified across 400 devices, measured utilizing 5 V peak-to-peak voltage, achieving electro-optical bandwidths up to 15.1 ± 1.8 GHz for 25μm-long devices. The results achieved are comparable to lab-based record-setting graphene devices of similar design and chemical vapor deposition graphene quality. By demonstrating the reproducibility of the results across hundreds of devices, this work resolves the bottleneck of graphene wafer-scale integration. Furthermore, CMOS-compatible processing enables co-integration of graphene-based devices with other photonics and electronics building blocks on the same chip, and for high-volume low-cost manufacturing.