Open circuit voltage reduction due to recombination at the heterojunction solar cell edge

Today to achieve high efficiency solar cells, the crystalline silicon (c-Si) heterojunction (HJ) represents one of the best available options. The key factor of its success is the high open circuit voltage (Voc) achievable, because of the excellent surface passivation due to the intrinsic amorphous silicon (a-Si:H) layers. During cells manufacturing, the a-Si:H film deposition is simultaneously performed on both c-Si wafer sides, and consequently also on the edges of the wafer. However, the wafer edges could result non-passivated in many cases such as the so-called shingling manufacturing route. Moreover, at laboratory level it is quite common to manufacture small area cells from larger wafers. When a silicon edge is left uncovered by cutting, a recombining region is created due to the silicon non-passivated surface. This, in principle, leads to a reduction in the Voc of the cell. Nevertheless, this is not experienced for large area cells cut in half but it is commonly observed that cutting silicon HJ edges results in a lowering in Voc. In this work we have analyzed the correlation between the Voc, the cell area and the recombining surface introduced by cutting the cell into a smaller one. We have monitored the Voc as a function of the cell area during time, and we also have investigated the possibility of a re-passivation of the cell edges by depositing a thick a-Si:H layer after masking the sun exposed cell surface, exploring different deposition conditions to avoid re-annealing of the existing a-Si:H layers.