NMOS逻辑
PMOS逻辑
dBc公司
材料科学
CMOS芯片
电气工程
光电子学
晶体管
功率消耗
相位噪声
低功耗电子学
功率(物理)
工程类
物理
电压
量子力学
标识
DOI:10.1109/iccs52645.2021.9697180
摘要
In this paper, an ultra-low-power injection-locked frequency tripler (ILFT) based on a current-reuse structure is proposed with SMIC 55-nm CMOS design kit. Different from the conventional structure with a cross-coupling pair of two NMOS transistors, a current-reuse structure is introduced, consisting of a single PMOS and NMOS transistors for the cross-coupling pair, resulting in ultra-low-power consumption. Meanwhile, we add a higher-order resonator based on the transformer to compensate for the fatal defect: narrow locking range (LR) due to low power consumption. In the simulation results, when injection at 0-dBm, the LR can reach 1.8 GHz (21.2–23 GHz, 8.1%) with only 3.09–3.80 mW core-power consumption. And output is locked at 22 GHz when injection at 7.33 GHz with 10.13 dBc/Hz @ 1MHz phase noise (PN) deterioration.
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