Toward 3nm overlay and critical dimension uniformity: an integrated error budget for double patterning lithography

Double patterning has emerged as the likely lithography technology to bridge the gap between water-based ArF immersion lithography and EUV. The adoption of double patterning is driven by the accelerated timing of the introduction of device shrinks below 40nm half pitch, especially for NAND flash. With scaling, increased device sensitivity to parameter variations puts extreme pressure on controlling overlay and critical dimension uniformity. Double patterning also makes unique demands on overlay and CDU. Realizing that there is no further increase in NA past the current 1.35 on the horizon, the focus has shifted from a straight shrink using the newest tool to learning how to reduce the effective k₁ through improvements to the tool's control of CDU and overlay, as well as innovative RET, mask, and process technology. In double patterning lithography, CDU and overlay are complex and entangled errors. In an approach where the pattern is split into two masks and recombined in successive lithography and etch steps, a line or space width is defined by edges placed at separate masks. In an approach where double patterning is achieved by self-aligned processes, CD error at the first sacrificial mask will translate into pattern placement errors in the final pattern. In all approaches, it is crucial to understand how these errors interact so that the combined effects can be minimized through proper tool controls, mask OPC and split algorithms, and process choices. Without aggressive actions, the complexity of this problem combined with the economic drawbacks of using multiple masking steps to define critical device layers threaten to slow overall device shrink rates. This paper will explore the main sources of critical dimension and overlay errors in double patterning lithography and will point out directions we may follow to make this an effective manufacturing solution.