Etch Mechanism Study in Gate Patterning for 14 nm Node and beyond FinFET Devices

In this work, two particular and interesting phenomena encountered in 14 nm gate mask etch including severe α-Si dummy gate top surface recess and reversely tapered Si3N4 mask profiles have been observed for the first time by using 193 nm lithography. Due to 3D topography of FinFET devices, the hard mask etch influences the final gate profile, notch formation and CD variation, which, in turn, impacts electrical performance and reliability of the devices. Therefore, fully understanding gate mask etch mechanism is a key to avoid device performance degradation. It is believed that local differential charging between the sidewall surface and feature bottom is responsible for the formation of etch failure associated with gate mask, because it induces deflected ions to cause enhanced ion etch behavior. We have proposed two simple process optimizations which not only can reduce dummy gate top surface recess but also help improve the anisotropy of gate mask etch. The patterning strategies presented in this paper are very useful and also offer a potentially universal method for the fabrication of advanced FinFET and various novel nanodevices in an efficient way.