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Die to Wafer Hybrid Bonding and Fine Pitch Considerations

菊花链 材料科学 互连 晶片测试 薄脆饼 引线框架 晶片键合 引线键合 电子工程 集成电路封装 芯片级封装 复合材料 光电子学 炸薯条 晶片切割 模具(集成电路) 计算机科学 纳米技术 半导体器件 电气工程 集成电路 工程类 计算机硬件 图层(电子) 电信
作者
Thomas Workman,Laura Mirkarimi,Jeremy Theil,G. G. Fountain,KM Bang,Bongsub Lee,Cyprian Uzoh,Dominik Suwito,Guilian Gao,P. Mrozek
出处
期刊:Electronic Components and Technology Conference 卷期号:: 2071-2077 被引量:19
标识
DOI:10.1109/ectc32696.2021.00326
摘要

Hybrid bonding is becoming increasingly important as the semiconductor industry plans for the next generation of packaging where high bandwidth architectures are required to achieve improved compute performance demands. The scalability challenges in solder-based interconnects at <; 35 μm pitch has fueled the adoption of hybrid bonding as a technology with enhanced scalability. The direct bond interconnect (DBI®) technology which was developed originally for wafer to wafer (W2W) applications has been extended to die to wafer (D2W) as DBI® Ultra. In this paper, we discuss the test results for a new die to wafer hybrid bonding test vehicle with an interconnect design of 2 μm pad on 4 μm pitch. The 8 mm by 12 mm chip contains daisy chain test structures ranging from 126,000 to 1,600,000 links. The component die wafers were singulated with conventional stealth dicing and then processed on tape frame for preparation of D2W bonding. The 2 μm bond pad requires sub-micron alignment accuracy within the pick and place tool for 100% alignment yield. However, due to bonder availability, our initial trials were bonded on a Besi Chameo Advanced bonder with an ISO 3 bonding environment and an alignment accuracy of +/- 3 μm (3 σ). The bond quality is characterized with C-mode scanning acoustic microscopy (CSAM), electrical resistance measurement, and cross-section microscopy analysis. The bond yield is shared as a function of bond defect density and electrical yield. Daisy chain yield and resistance versus misalignment for the fine pitch test vehicle are compared to test vehicles having a 10 μm pad on 40 μm pitch. The implications of the 10x pitch shrink on process control from wafer and die fabrication are discussed.
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