Noise Immune, Low-Skew, Pulse Width Retainable Analog Glitch-Filter

Slow, noise-prone IC interfaces such as I2C and SPI require input buffers with a glitch filter circuit to suppress input spikes of a given pulse width. This glitch filter is conventionally implemented as an analog RC circuit whose resistor and capacitor values are chosen according to the pulse width to be suppressed. Such a topology suffers from duty cycle distortion, pulse clipping and supply noise susceptibility — issues that could produce both functional as well as critical timing failures at system level. Our work addresses these issues by proposing an analog glitch filter that employs a combination of feed-back and feed-forward circuit elements, with minimal area overhead with respect to conventional schemes.