VeNNus: An Artificial Intelligence Accelerator Based on RISC-V Architecture

Developing prototypes for systems with custom chips is the most recent advancement in accelerator-centric architectures. The development of such prototype is a challenging task but with the emergence of new open-source software's and hardware's help in addressing this challenge to an extent by reducing implementation, design and effort. With increasing utility of Artificial Intelligence (AI) in various applications, there are great benefits to be reaped from faster training and computation of neural networks. The objective of this research is to develop an open-source architecture for acceleration of AI applications. We studied in detail the existing and available AI accelerators, and understood their key features. Their key functionalities were incorporated in the design of the VeNNus processor. This paper describes the architecture of the VeNNus processor, which uses the RISC-V Instruction Set Architecture (ISA). RISC-V ISA offers benefits such as flexibility, lower costs and high efficiency. However, to further improve the performance and energy efficiency of our Artificial Intelligence (AI) accelerator, 16 custom vector instructions were added in extension to the RISC-V ISA. The VeNNus processor includes redundant Arithmetic-Logic Units (ALUs), and uses quantization of training weights to 8-bit integers to deliver better performance, driving higher throughput. With the processor using vector instructions and quantization, we anticipate good acceleration of deep neural networks. The vital benefits and challenges faced with the RISC-V instruction set are described in this paper.