Multi-gate BCAT Structure and Select Word-line Driver in DRAM for Reduction of GIDL

In this article, we evaluate gate induced drain leakage that affects the refresh time of buried cell array transistor DRAM cells. We proposed a multi-gate BCAT structure to minimize gate induced drain leakage and modified the select word-line circuit to operate multi-gate buried cell array transistor by adding only one PMOS. In the multi-gate structure, by changing the gate voltage, the work function of the metal gate was adjusted to effectively mitigate the electric field formed in the drain region by approximately four orders. As an adopting multi-gate structure, band to band tunneling is suppressed and gate induced drain leakage current is reduced. We verified that the dual-gate structure had less leakage current than the poly-Si BCAT using the TCAD simulation. The reduction of leakage according to the number of gates is inferred by confirming the reduction in GIDL of the three-gate structure compared with the dual-gate structure. Furthermore, the SPICE simulation confirmed that the proposed select word-line circuit transmits different optimized voltages to multiple gates when it is off than while transferring the same voltage when on. This structure can also be extended for application to other DRAM structures, such as the vertical structure and 3D-stacked DRAMs.