Self-Aligned Edge Contact Process for Fabricating High-Performance Transition-Metal Dichalcogenide Field-Effect Transistors

The persistent challenges encountered in metal-transition-metal dichalcogenide (TMD) junctions, including tunneling barriers and Fermi-level pinning, pose significant impediments to achieving optimal charge transport and reducing contact resistance. To address these challenges, a pioneering self-aligned edge contact (SAEC) process tailored for TMD-based field-effect transistors (FETs) is developed by integrating a WS2 semiconductor with a hexagonal boron nitride dielectric via reactive ion etching. This approach streamlines semiconductor fabrication by enabling edge contact formation without the need for additional lithography steps. Notably, SAEC TMD-based FETs exhibit exceptional device performance, featuring a high on/off current ratio of ∼108, field-effect mobility of up to 120 cm2/V·s, and controllable polarity─essential attributes for advanced TMD-based logic circuits. Furthermore, the SAEC process enables precise electrode positioning and effective minimization of parasitic capacitance, which are pivotal for attaining high-speed characteristics in TMD-based electronics. The compatibility of the SAEC technique with existing Si self-aligned processes underscores its feasibility for integration into post-CMOS applications, heralding an upcoming era of integration of TMDs into Si semiconductor electronics. The introduction of the SAEC process represents a significant advancement in TMD-based microelectronics and is poised to unlock the full potential of TMDs for future electronic technologies.