Multi-Chip Stacked Memory Module Development using Chip to Wafer (C2W) Hybrid Bonding for Heterogeneous Integration Applications

The present study focuses on multi-chip stacked memory module development, and it encompasses a comprehensive overview of critical aspects, key learnings, encountered challenges, and the corresponding mitigation strategies. It initiates the formulation of test vehicle designs and progresses through mechanical simulations, wafer fabrication, and meticulous materials selection. It delves into the complexities of chip-to-wafer (C2W) hybrid bonding and assembly processes for hybrid bonding module development. The test vehicle design is tailored to accommodate a substrate along with two logic and memory stacked test chips. Extensive finite element analysis (FEA) simulations are conducted to comprehend and enhance the integrity of bonded dielectric layers and Cu pads, considering diverse designs, materials, and process parameters of the C2W-HB processes. For test chip stacking, chip design, dielectric materials selection, wafer fabrication methodology, chip warpage, and hybrid bonding approach play a critical role. The process integration, dielectric stack, and dielectric deposition recipes have been fine-tuned to limit the thin memory chip warpage to less than 60 μm, ensuring successful chip stacking and hybrid bonding. Several fabrication processes and modules have been optimized to fabricate memory wafers with double-side hybrid bonding pads and TSV structures using low-temperature dielectric materials on the backside. Following C2W hybrid bonding and molding, under-bump metallization (UBM) fabrication is established on the substrate wafer backside for electrical testing and board-level assembly purposes. Electrical testing outcomes and yields at the UBM match those obtained from wafer front-side testing.