Strengthened Complementary Metal–Oxide–Semiconductor Logic for Small-Band-Gap Semiconductor-Based High-Performance and Low-Power Application

Silicon-based complementary metal–oxide–semiconductor (CMOS) has been the mainstream logic style for modern digital integrated circuits (ICs) for decades but will meet its performance limits soon. Extensive investigations have thus been carried out using other semiconductors, especially those with extremely high carrier mobility. However, these materials usually have small or even zero band gap, which leads inevitably to large leakage current or voltage loss in ICs based on these semiconductors. In this work, we propose and demonstrate a strengthened CMOS (SCMOS) logic style using modified field-effect transistors (FETs) to solve this problem, that is, to achieve high performance, utilizing the high carrier mobility in these materials, and to reduce the current leakage resulting from their small band gap. Conventional CMOS FETs are modified to have an asymmetric structure where an additional assistant gate is introduced near the drain to further lower the potential barrier in on-state and to increase the barrier in off-state. SCMOS ICs are constructed using these modified asymmetric CMOS FETs, which demonstrate perfect rail-to-rail output with negligible voltage loss and 3 orders of magnitude suppression of the static power consumption and an operating speed similar to or even higher than that of CMOS ICs. Here, SCMOS is demonstrated using carbon nanotubes, but, in principle, this logic style can be used in ICs based on any small-band-gap semiconductors to provide simultaneously high performance and low power consumption.