The Parasitic Latch-Up Path From Substrate P⁺ Guard Ring to the NMOS in Deep N-Well Operating With Negative Voltage Sources

For implanted neuro-modulation applications, the electrical stimulation circuits had been designed to be operating with positive and negative voltage sources. To support the circuit operation with negative voltage source, the deep n-well (DNW) layer has been added into the CMOS process to isolate the devices with negative voltage from the common grounded p-type substrate. In chip layout, the guard ring of grounded P+ diffusion is often drawn to surround the whole DNW layer for latch-up prevention and/or noise reduction. However, in the stimulation circuits operating with negative voltage sources, a parasitic latch-up path from the grounded p+ guard ring (p+ GR) to the N+ diffusion of the stacked-nMOS (STnMOS) biased at negative voltage source in a DNW may cause latch-up issue to the stimulation circuits. In this letter, such a parasitic latch-up path is first reported in the article. From the experimental results verified in a 0.18- $\mu \text{m}$ 1.8-V/3.3-V CMOS process, the holding voltage (Vh) of such a parasitic latch-up path is related to the spacing between the p+ GR and the N+ diffusion of STnMOS, as well as to the series resistance that connect the isolation ring of DNW to ground. Furthermore, the magnitude of Vh is decreased when the operating temperature is increased.