Performance Comparison of SRAM Designs Implemented with Silicon-On-Insulator Nanosheet Transistors and Bulk FinFETs

This study compares six-transistor (6T) static random access memory (SRAM) implemented with state-of-the-art bulk FinFETs and silicon-on-insulator (SOI) gate-all-around nanosheet transistors (NSFETs) for G40M16/T2 (2 nm) process node. Compared to the FinFET 6T SRAM whose pull-up (PU), pass-gate (PG), and pull-down (PD) transistor footprint (device layout width) ratio can only be either PU:PG:PD = 1:1:2 or 1:2:2, the PU:PG:PD of NSFET SRAM can be 1:α:2, where α can be any number between 1 and 2 owing to the adjustable channel widths of PG transistors . The optimal read and write static noise margin (RSNM and WSNM) design is PU:PG:PD = 1:1.458:2, where the RSNM = WSNM = 171 mV, which is 14% and 51% higher than the minimum RSNM and WSNM values of 1:1:2 and 1:2:2 FinFET SRAMs respectively. Moreover, because the entire device above the SOI substrate of the SOI NSFET can conduct current, its drive current is 109% higher than that of bulk FinFET, in which the part of the device above the silicon substrate forms a punch-through stopper, which does not contribute to the conductive current. In addition, the read/write access time of NSFET SRAM is 49%/7% faster than that of the bulk FinFET SRAM under a 1:2:2 design owing to the higher drive current.