A TDC With Integrated Snapshot Circuit and Calibration in 28nm CMOS

This paper presents a 135 ps dynamic range, 5.45 ps effective resolution 2D Vernier time-to-digital converter for use in an all-digital phase-locked-loop. The matrix readout array limits the number of delay cells necessary by using all taps of the delay lines. A full calibration scheme is presented. It calibrates the system against PVT variations and maintains and favors a linear operation over achieving a specified resolution. The proposed architecture is fabricated in a 28 nm CMOS technology and consumes 360 μW at 0.9 V supply voltage and 55 MS/s conversion rate.