Surface Charge Migration in SiC Power MOSFETs Induced by HVDC-H3TRB Testing

Simultaneous high-humidity, high-temperature, reverse bias testing, otherwise known as H3TRB testing, is conducted to compare the accelerated failure of vertical 1700-V silicon carbide MOSFETs provided by two well-known manufacturers. A pronounced drain-to-source leakage is observed in the tested devices from only one of the manufacturers. Interrupted test measurements reveal that the degradation mode occurs relatively quickly (i.e., < 100 hours) for the failed devices. A post-test bake-out returns all the tested devices to nominal behavior and strongly suggests that the failure mechanism is associated with surface charge buildup in or below the passivation layer. Scanning electron microscopy and scanning capacitance microscopy imaging reveal significant design differences in the edge termination structure for each device set. The difference in design choice demonstrates how humidity robustness may be achieved through device-level surface charge mitigation strategies rather than relying on a hermetic encapsulant.