材料科学
电介质
生产线后端
无定形固体
硅
光电子学
CMOS芯片
非晶硅
纳米技术
晶体硅
结晶学
化学
作者
Juxin Yin,Fuqiang Zheng,L. Shu,Yan Zhang,Jingru Shen,Wanli Yang,Yunlong Li,Xuqing Zhang,Dawei Gao
标识
DOI:10.1109/cstic61820.2024.10531875
摘要
In order to better adapt to ever-evolving manufacturing processes and improve critical dimension (CD) control in CMOS Back End of Line (BEOL), an investigation using amorphous silicon (a-Si) as the dry etch hard mask in low-k dielectric patterning is performed, which targets for a higher selectivity toward low-k dielectric than the conventional metal hard mask.
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