Design space exploration and power optimization of STT MRAM using trimmed fin Asymmetric FinFET

The switching current requirement of magnetic tunnel junction (MTJ) in STT MRAM is highly asymmetric. This results in unnecessary higher power dissipation due to excess write current in one direction. To tackle this issue, we present a novel STT MRAM cell that utilizes the trimmed fin asymmetric FinFET (A-FinFET) as an access device, which has an impressive asymmetry in the bidirectional current and smaller gate capacitance compared to the symmetric FinFET device. Our approach begins with the development of a SPICE model for the A-FinFET, achieved by calibrating the BSIM-CMG model to replicate the characteristics of the A-FinFET. Further, it is used to evaluate the performance of STT MRAM using a comprehensive analysis from the cell to the architecture level, employing HSPICE and NVsim tools. The findings indicate significant enhancements with the proposed design, leading to a remarkable 18 % reduction in power consumption without compromising area. Additionally, the effective area of wordline drivers is reduced by 11 % compared to the symmetric device implementation. • A novel STT-MRAM cell employing trimmed fin asymmetric FinFET (A-FinFET) as an access device. • Calibration of the BSIM-CMG model to replicate the characteristics of the A-FinFET. • Comprehensive analysis from the cell to the architecture level, employing HSPICE and NVsim tools. • Remarkable 18 % reduction in power consumption without compromising area. • Effective area of word line drivers is reduced by 11 % compared to the symmetric device implementation.