Signal and Power Integrity Performance of CoWoS-R in Chiplet Integration Applications

CoWoS-R RDL interposer technology is a key enabling solution to provide low parasitic interconnects between chiplets for high performance computing (HPC) applications. In the study, UCIe IO circuit with data rate up to 32GT/s is implemented on the CoWoS-R technology, the solutions to mitigate the crosstalk of the high-speed transmission line from RDL line arrangements are explored for signal integrity (SI) performance. For power integrity (PI), the power delivery network (PDN) impedance for the RDL interposer structure is studied. To reduce the impedance, integrated passive device (IPD) capacitor is applied. The IPD placed on the bottom of the RDL interposer could provide better impedance performance with 23% reduction at 100 MHz.