Patterning optimization for single mask bit-line-periphery and storage-node-landing-pad DRAM layers using 0.33NA EUV lithography at the resolution limit

To continue the future of dynamic random-access memory (DRAM) manufacturing with EUV and high NA EUV, alternative techniques for nanofabrication are required to reduce the cost and simplify the processes. In this report, we present the results of the development of a single mask solution with 0.33NA EUV lithography for two important layers, bit-line-periphery (BLP) and storage-node-landing-pad (SNLP), in DRAM manufacturing. The methodology has been established for our examination and assessment of the process window (PW) of the critical dimensions (CD) and the defectivity of the SNLP and BLP layers. Based on this methodology, a pitch 34nm DRAM has been optimized with the spin-on metal oxide resist (MOR) and dark field of a binary mask. We obtained the large overlapping PW of CDs (with a depth of focus of 119nm and an exposure latitude of 25% at a dose-to-size of 89.4mJ cm^-2) in the free-defect ranges (20mJ cm^-2). We achieved around ~22% dose reduction using the same processes with spin-on MOR applied to the new design of a low-n mask. We observed a pitch of 32nm SNLP and BLP with a single mask layer due to a low-n mask. Additionally, the process window discovery (PWD) methodology for defect inspection in the large area of SNLP and BLP shows good progress which can be applied for optimized conditions. We believe that our results show the resolution limit of 0.33NA lithography for the single mask print SNLP-BLP and 0.55NA EUV is needed for the next generations of DRAM.