Programmable low-frequency divider in 180-nm CMOS technology

This paper presents the design and measurements of a programmable frequency divider that converts the input clock of 32 kHz to 1 Hz. The circuit is designed, simulated and the layout is drawn in Cadence simulation environment. The binary counter used in the circuit design is synchronous counter with asynchronous reset. The output frequency drift is measured and compared with simulation results for the varying supply voltage from 1.1 to 1.3 V and temperature from -40°C to 80°C.