Overlay breakdown methodology on immersion scanner

In the last years a flourishing number of techniques such as High Order Control or mappers have been proposed to improve overlay control. However a sustainable improvement requires sometimes understanding the underlying causes of the overlay limiting factors in order to remove them when possible or at least to keep them under control. Root cause finding for overlay error is a tough task due the very high number of influencing parameters and the interaction of the usage conditions. This paper presents a breakdown methodology to deal with this complexity and to find the contributors of overlay error variation. We use a Partial Least Squares (PLS) algorithm to isolate the key contributors for correctable terms and a field-to-field linear regression technique to highlight the main causes of residuals. We present a study carried out on 45nm CMOS contact-gate overlay over 687 production wafers exposed in an ASML TWINSCAN XT:1700i Immersion scanner. We present the results of the correlations with the 180 process and equipment variables used for this study. For each isolated contributor we propose an explanation of the underlying physical phenomenon and solutions.