有效位数
逐次逼近ADC
电容器
噪声整形
电子工程
计算机科学
噪音(视频)
带宽(计算)
模数转换器
功率消耗
电压
功率(物理)
电气工程
工程类
物理
电信
人工智能
图像(数学)
量子力学
CMOS芯片
作者
Zhiyuan Dai,Hang Hu,Yongzhen Chen,Fan Ye,Junyan Ren
标识
DOI:10.1109/mwscas.2018.8624111
摘要
Successive approximation register Analog-to-digital converter (SAR ADC) with a passive noise-shaping modulator is an appropriate choice to increase the ENOB and save power consumption compared with conventional SAR ADC. This paper proposed a third-order noise-shaping SAR ADC with high speed switches in modulators to complete the charge sharing for reducing the time cost of noise shaping process in one sampling cycle and used a foreground calibration to calibrate the value of the capacitors in DAC array. The whole ADC can realize 12.11-Bit ENOB in 8MHz bandwidth (BW).
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