NMOS逻辑
PMOS逻辑
MOSFET
阈值电压
绝缘体上的硅
材料科学
灵敏度(控制系统)
光电子学
过驱动电压
晶体管
电压
电气工程
兴奋剂
电子工程
硅
工程类
作者
M. Sherony,L.T. Su,J.E. Chung,Dimitri A. Antoniadis
出处
期刊:IEEE Electron Device Letters
[Institute of Electrical and Electronics Engineers]
日期:1995-03-01
卷期号:16 (3): 100-102
被引量:29
摘要
The threshold voltage sensitivity, of fully depleted SOI MOSFET's to variations in SOI silicon film thickness was examined through both simulation and device experiments. The concept of designing the channel V/sub th/ implant to achieve a constant dose within the film, rather than a constant doping concentration, was studied for a given range of film thicknesses. Minimizing the variation in retained dose reduced the threshold voltage sensitivity to film thickness for the range of t/sub si/ examined. One-dimensional process simulations were performed to determine the optimal channel implant condition that would reduce the variation in retained dose using realistic process parameters for both NMOS and PMOS device processes. SOI NMOS transistors were fabricated. The experimental results confirmed the simulation findings and achieved a reduced threshold voltage sensitivity.< >
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