材料科学
干法蚀刻
反应离子刻蚀
纳米线
微电子机械系统
蚀刻(微加工)
光电子学
感应耦合等离子体
图层(电子)
各向同性
各向同性腐蚀
晶体管
纳米技术
等离子体
电气工程
光学
物理
工程类
电压
量子力学
作者
Junjie Li,Wenwu Wang,Yongliang Li,Na Zhou,Guilei Wang,Zhenzhen Kong,Jianyu Fu,Xiaogen Yin,Chen Li,Xiaolei Wang,Hong Yang,Xueli Ma,Jing Han,Jing Zhang,Yijun Wei,Tairan Hu,Tao Yang,Junfeng Li,Huaxiang Yin,Huilong Zhu,Henry H. Radamson
标识
DOI:10.1007/s10854-019-02269-x
摘要
On approach towards the end of technology roadmap, a revolutionary approach towards the nanowire transistors is favorable due to the full control of carrier transport. The transistor design moves toward vertically or laterally stacked Gate-All-Around (GAA) where Si or SiGe can be used as channel material. This study presents a novel isotropic inductively coupled plasma (ICP) dry etching of Si1−xGex (0.10 ≤ x ≤ 0.28) in SiGe/Si multilayer structures (MLSs) with high selectivity to Si, SiO2, Si3N4 and SiON which can be applied in advanced 3D transistors and Micro-Electro-Mechanical System (MEMS) in future. The profile of SiGe etching for different thicknesses, compositions and locations in MLSs using dry or wet etch have been studied. A special care has been spent for layer quality of Si, strain relaxation of SiGe layers as well as residual contamination during the etching. In difference with dry etching methods (downstream remote plasma), the conventional ICP source in situ is used where CF4/O2/He gas mixture was used as the etching gas to obtain higher selectivity. Based on the reliability of ICP technique a range of etching rate 25–50 nm/min can be obtained for accurate isotropic etching of Si1−xGex, to form cavity in advanced 3D transistor processes in future.
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