Characterization of Packaging‐Induced Stress Distributions for Small‐Scale Silicon Chips

Abstract This report shows packaging‐induced stress distribution of a small‐scale silicon chip encapsulated by a Small‐Outline Nonleaded package. The proposed method made it possible to visualize the stress distribution chart for a chip about 1.0 mm 2 in size with high accuracy, even when the chip has only four pads. It is found that the stress was generated during resin molding, as determined from stress measurement during the middle of the packaging process. In addition, the impact of filler particle size and position in Epoxy Molding Compounds on the local stress of the chip surface is revealed. The compressive stresses were found to be greatest at the center of the chip and gradually decrease toward the edges. Also, the results for die pad structure produced a characteristic distribution chart in which the central area of the silicon chip has a smaller stress gradient. The impact of high‐temperature storage test on residual stress is also discussed. © 2020 Institute of Electrical Engineers of Japan. Published by Wiley Periodicals LLC.