ATLaS: Automatic Detection of Timing-based Information Leakage Flows for SystemC HLS Designs

In order to meet the time-to-market constraint, High-level Synthesis (HLS) is being increasingly adopted by the semiconductor industry. HLS designs, which can be automatically translated into the Register Transfer Level (RTL), are typically written in SystemC at the Electronic System Level (ESL). Timing-based information leakage and its countermeasures, while well-known at RTL and below, have not been yet considered for HLS. The paper makes a contribution to this emerging research area by proposing ATLaS, a novel timing-based information leakage flows detection approach for SystemC HLS designs. The efficiency of our approach in identifying timing channels for SystemC HLS designs is demonstrated on two security-critical architectures which are shared interconnect and crypto core.