A Machine Learning Approach for Predicting the Difficulty of FPGA Routing Problems

In this paper, we present a Machine Learning (ML) Mixture of Experts (MoE) technique to predict the number of iterations needed for a Pathfinder-based FPGA router to complete a routing problem. Given a placed circuit, our technique uses features gathered on each routing iteration to predict if the circuit is routable and how many more iterations will be required to successfully route the circuit. This enables early exit for routing problems which are unlikely to be completed in a target number of iterations. Such early exit may help to achieve a successful route within tractable time by allowing the user to quickly retry the circuit compilation with a different random seed, a modified circuit design, or a different FPGA. We demonstrate our predictor in the VTR 8 framework; compared to VTR's predictor, our ML predictor incurs lower prediction errors on the Koios Deep Learning and Titan23 benchmark suites. Based on our tests, equipping VTR with our ML predictor would reduce time wasted on unroutable designs by 31% while also allowing 28% more routable designs to be completed.