A Two-stage Dynamic Comparator with Low Delay and Low Offset

Low delay and low offset comparators are crucial in many fields such as science, medicine, and engineering that require high-precision measurement and data collection, as they do not introduce large errors or time delay. Based on the SMIC 40 nm CMOS process, a two-stage dynamic comparator with low delay and low offset is designed. The circuit uses a high gain cross coupled operational amplifier to make the comparator regenerate faster and reduce the delay under a small input voltage difference; The offset voltage of the preamplifier stage in the comparator is eliminated by adding an offset calibration circuit, and the offset of the comparator will be further reduced by using a reset switch. Under the control of 1.2 V power supply voltage and 500 MHz clock, the delay of the comparator is about 42 ps. The average power consumption is about 150 μW. The offset voltage obtained by 200 Monte Carlo simulations is about 0.35 mV.