计算机科学
可扩展性
调度(生产过程)
正确性
分布式计算
可预测性
统一内存访问
嵌入式系统
并行计算
内存管理
操作系统
半导体存储器
量子力学
物理
经济
程序设计语言
运营管理
作者
Zuhua Jiang,Kecheng Yang,Neil Audsley,Nathan Fisher,Weisong Shi,Zheng Dong
标识
DOI:10.1145/3489517.3530612
摘要
In real-time embedded computing, time-predictability and performance are required simultaneously by memory transactions. However, with increasingly more elements being integrated into hardware, memory interconnects become a critical stumbling block to satisfying timing correctness, due to lack of hardware and scheduling scalability. In this paper, we propose a new hierarchically distributed memory interconnect, BlueScale, managing memory transactions using identical Scale Elements, which ensures hardware scalability. The Scale Element introduces two nested priority queues, achieving iterative compositional scheduling for memory transactions, guaranteeing transaction tasks' scheduling schedulability. Associated with the new architecture, a theoretical model is established to improve BlueScale's real-time performance.
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