High Speed Column Level ADC Design with TDC Technology for CMOS Image Sensor

A high-speed column-level ADC for CMOS image sensors is proposed in this paper, which uses a fully parallel two-step structure combined with TDC technology. The proposed circuit is designed and verified based on 55nm CMOS process. Under the design environment of 3.3 V analog voltage, 1.2V digital voltage, 250 MHz clock frequency and 1.5V input signal range, the signal-to-noise-distortion ratio (SNDR) of the 12-bit ADC reaches 68.272 dB, the DNL is +0.8/−0.8LSB, and the INL is +1.47/−1.74LSB. The power consumption of the column circuit is 72 μW and the switching time is 370 ns. It provides an efficient column-level ADC design scheme for high frame rate and large area array CMOS image sensors.