Methods for noise margin analysis of conventional 6 T and 8 T SRAM cell

SRAM is one of the essential components for portable devices which contributes significantly and determines the overall device performance. This paper analyzes the methods for calculating noise margin of conventional 6 transistor (6 T) and 8 transistor (8 T) SRAM cell. For calculation of noise margins in memory cell, this paper considered butterfly analysis and noise-curve methods. From the simulation results obtained from the above-mentioned method, the findings shows that 8 transistor SRAM cell provides higher read noise margin than 6 transistor SRAM cell. The aim of this paper is to verify and validate butterfly analysis and noise-curve methods for calculation of noise margins in memory cells. From the simulation data it is observed that major limitation of using butterfly analysis to measure SNM is the inability of measuring SNM using inline techniques and it’s time consuming and complex process. It may sometimes give inaccurate/ misleading results due to computational error. Whereas, N-curve method for SRAM cell analysis is used for inline testing and also provides additional information regarding current and voltage stability. Additionally, the N-curve can be utilized to perform an analysis of the power dissipation by the SRAM cell while it is undergoing read or write operation. Using 90 nm technology file, cadence virtuoso EDA tools simulate both 6 transistor and 8 transistor SRAM cells.