A Low-Ripple Resistor-Less Hybrid Loop Filter based PLL in 3nm FinFET

A resistor-less hybrid loop filter is introduced as part of a 12. 6GHz$\sim$14.5GHz low-jitter PLL in TSMC 3nm FinFET technology. The hybrid loop filter eliminates the large integration capacitor and resistor by leveraging a digitized integral path (IPATH) and a differential sample-and-hold (S/H) proportional path (PPATH) separately. While saving much area and gaining flexible loop adjustments, the scheme significantly improves the control voltage ripple, as well as in-band noise. The PLL achieves 56fs-rms (1kHz to 100MHz) and 72fs-rms (full band) random jitter @13.28GHz, dissipating 18. 6mW from 0. 875V supply. The simulated reference spurious tone can be suppressed to be $\lt-98$dBc with a comparator input offset of $\sim$5mV.