This paper presents a low noise operational amplifier with noise optimization and reduction techniques. It consists of a folded-cascode amplifier and a class-AB output stage with a simple minimum selector. The input-referred noise of an input transistor can be optimized through utilization of the relationship between input parasitic capacitance and flicker noise. The other main noise sources in a folded-cascode amplifier are reduced by increasing the size, adding resistors or by stacking FETs at the cascade biasing circuitry. The proposed amplifier is implemented in a 0.18-μm CMOS process.