22.2 A 69.5mW 20GS/s 6b time-interleaved ADC with embedded time-to-digital calibration in 32nm CMOS SOI

Low-power time-interleaved ADCs with high sampling rates of over 10GS/s are in high demand for wireline communication systems. However, the time-interleaved channels suffer from process mismatch, particularly for timing skew. Although a power-consuming two-rank track-and-hold (T/H) can prevent such timing-skew problems, distributed T/Hs can be used for lower-power operation with timing-skew calibration to meet the skew specifications of 200fs _rms for 6b resolution and 10GHz input signals. Instead of using software calibration with Fourier analysis [1-3], requiring a special input reference signal [4], or relying on the statistics of the input signal [5], this work presents a low-complexity on-chip background calibration technique to reduce gain, offset, and delay mismatches between channels. This enables small-size transistors to be used in comparators and clock delivery circuits to avoid serious noise coupling and save considerable power for such an ultra-high-speed system. The presented 8-way time-interleaved 20GS/s 6b ADC achieves an SNDR of 30.7dB at Nyquist and consumes only 69.5mW.