材料科学
多晶硅
量子隧道
闪存
压力(语言学)
与非门
闪光灯(摄影)
光电子学
晶体管
电气工程
电压
逻辑门
纳米技术
薄膜晶体管
计算机科学
物理
图层(电子)
嵌入式系统
工程类
光学
语言学
哲学
作者
Dong-Hyun Kim,Kihoon Nam,Chanyang Park,Hyunseo You,Min Sang Park,Yunsu Kim,S. B. Park,Rock‐Hyun Baek
标识
DOI:10.1016/j.sse.2024.108927
摘要
This study investigated the relationship between mechanical stress and program efficiency in three-dimensional (3D) NAND flash memory devices. A stacked memory array transistor (SMArT) 3D NAND flash structure was modeled using a technology computer-aided design (TCAD) simulation. The mechanical stress distribution in the device depended on the deposition temperature (TD) of the constituent material. In particular, the TD of tungsten (TD,W) dominated the mechanical stress. The tensile stress on the polycrystalline silicon (poly-Si) channel increased as the TD,W decreased, and the compressive stress on the tunneling oxide (Tox) decreased. Consequently, the barrier height between Tox and poly-Si, and the effective electron mass decreased as the electric field in the Tox increased. These changes significantly increased the Fowler-Nordheim (FN) tunneling process and program efficiency, indicating the crucial performance of 3D NAND flash. Moreover, the mechanical stress caused by the differences in TD,W improved the program efficiency at a lower program voltage (VPGM). Therefore, a change in the mechanical stress based on decreasing TD,W improved the program efficiency through a higher FN tunneling process.
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