MOSFET
JFET公司
材料科学
电气工程
光电子学
肖特基二极管
二极管
肖特基势垒
场效应晶体管
饱和电流
晶体管
电压
工程类
作者
Jaeyeop Na,Minju Kim,Kwangsoo Kim
出处
期刊:Energies
[Multidisciplinary Digital Publishing Institute]
日期:2022-09-22
卷期号:15 (19): 6960-6960
被引量:1
摘要
Built-in freewheeling diode metal–oxide–semiconductor field-effect transistors (MOSFETs) that ensure high performance and reliability at high voltages are crucial for chip integration. In this study, a 4H–SiC built-in MOS-channel diode MOSFET with a center P+ implanted structure (CIMCD–MOSFET) is proposed and simulated via technology computer-aided design (TCAD). The CIMCD–MOSFET contains a P+ center implant region, which protects the gate oxide edge from high electric field crowding. Moreover, the region also makes it possible to increase the junction FET (JFET) and N-drift doping concentration of the device by dispersing the high electric field. Consequently, the CIMCD–MOSFET is stable even at a high voltage of 3.3 kV without static degradation and gate oxide reliability issues. The CIMCD–MOSFET also has higher short-circuit withstanding capability owing to the low saturation current and improved switching characteristics due to the low gate-drain capacitance, compared to the conventional MOSFET (C–DMOSFET) and the built-in Schottky barrier diode MOSFET (SBD–MOSFET). The total switching time of a CIMCD–MOSFET is reduced by 52.2% and 42.2%, and the total switching loss is reduced by 67.8% and 41.8%, respectively, compared to the C–DMOSFET and SBD–MOSFET.
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