作者
Meng Huang,Shufang Si,Zheng He,Ying Zhou,Sijia Li,Hong Wang,Jinying Liu,Dongsheng Xie,Mengmeng Yang,Kang You,Chris Choi,Yi Tang,LI Xiao-jie,Shi-Bing Qian,Xiaodong Yang,Lei Hou,Weiping Bai,Zhongming Liu,Yanzhe Tang,Qiong Wu,Yanqin Wang,Tao Dou,Jake Kim,Guilei Wang,Jie Baisp,Ayuse Takao,Chao Zhao,Abraham Yoo
摘要
Continuous shrinking of dynamic random access memory $\langle$DRAM) feature size will inevitably hit unsurmountable barriers, such as sub-10 nm patterning issues, ultra-high aspect ratio (HAR) capacitor and narrow sensing margin, etc. One candidate of promising solutions is the innovation in architecture with three-dimensional (3D) horizontally stacked transistors with capacitors, similar with a 3D NAND-like architecture. However, the process integration scheme and circuit simulation on the 3D Stackable DRAM architecture have been barely reported. In this paper, we systematically introduced a 3D DRAM architecture, integration scheme for the first time. Then we further performed circuit simulation studies on the 3D DRAM, which in return confirm the feasibility of our proposed architecture and show great prospect in DRAM core timing optimization.