A 12-bit 3-GS/s Tri-Segmented Current Steering DAC with A Complementary Switching Technique

In this paper, a 12-bit 3-GS/s tri-segmented structure current steering digital-to-analog converter (CSDAC) with a complementary switching current source is designed and simulated in 130 nm CMOS technology. This work introduces the complementary switch current source within the CSDAC to reduce the effect of input code dependency on the CSDAC output impedance to enhance its linearity and harmonic distortion. The achieved SFDR which is the indication of DAC linearity ranges from 96.2 dB near low frequency and degraded up to 77.78 dB at 1.5 GHz. The signal-to-noise and distortion ratio SNDR ranges from 74 dB to 72.2 dB at the maximum input frequency. Additionally, The proposed design achieves an ENOB that ranges from 11.95-bit to 11.7-bit across the entire frequency band.