A 2.72 μ$$ \upmu $$s row conversion time 11‐bit column‐parallel single‐slope analog to digital converter with differential‐clocks‐assisted time to digital converter interpolation for complementary metal oxide semiconductors image sensor

Abstract This paper presents an innovative readout scheme that utilizes a pair of differential‐clocks‐assisted time‐to‐digital converter (DCA‐TDC) in CMOS image sensors (CISs). The DCA‐TDC utilizes only half the number of ordinary TDC delay chain units by employing a binary‐weighted search algorithm to determine the most significant bit (MSB) for fine quantization of a single‐slope analog‐to‐digital converter (SS ADC). Additionally, the layout area and dynamic power introduced by the improved DCA‐TDC delay chain are halved compared to an ordinary TDC delay chain. The proposed SS ADC is designed and simulated using the 0.11 m standard CMOS proces, achieving an 11‐bit ADC with a column‐level power consumption of 65.4 W, and a row conversion time of 2.72 s, within a design environment featuring an analog voltage of 3.3 V, a digital voltage of 1.5 V, a clock frequency of 62.5 MHz, and a temporal resolution of 500 ps. Furthermore, this design achieves an effective number of bits (ENOB) of 10.71 and a figure of merit (FoM) of 110.5 fJ/step. By interpolating a DCA‐TDC, the quantization speed is enhanced compared to traditional SS ADCs, presenting an effective solution for high‐frame‐rate CIS implementations.