Advanced Packaging Technology Platforms for Chiplets and Heterogeneous Integration

As Moore’s law continues to challenge the foundry companies to increase transistor density, the exponential cost of silicon scaling has created an inflection point for the industry. The high development cost and lower yields for advanced Si nodes are challenging designers to look for new ways of disaggregating monolithic SoC. Die partitioning and chiplets integration provides more flexible mix-and-match systems to accelerate performance and power efficiency. It is driving the development of advanced packaging technology to enable chiplets with separate designs and different manufacturing process nodes within a single package for yield improvement, IP reuse, performance and cost optimization, as well time to market reduction. Meanwhile, heterogeneous integration enables system co-optimization by separated out different functions, such as logic, memory, analog, power, and integrated them into a system. Chiplets and heterogeneous integration through the advanced packaging technology have provided the solutions to fulfill the demands for high performance, high power efficiency, small form factor and low cost across multiple industry market segments including server, networking, graphics, mobile and telecom infrastructure.In this paper, a series of RDL based Vertically Integrated Packaging (ViPack) solutions have been introduced for chiplets and heterogeneous integration that continue to evolve to meet various challenges and various market application demands. These include Fan-Out Chip-on Substrate (FOCoS), Fan Out Chip on Substrate embedded Bridge (FOCoS-B)) and Fan Out Package-on-Package (FOPoP). Meanwhile, the electrical performance and signal integrity for multiple chiplets integration for FOCoS solutions are also discussed. Finally, the comparison on warpage and reliability validation for chiplets integration among different FOCoS solutions have been elaborated.