现场可编程门阵列
系列(地层学)
动态范围
航程(航空)
计算机科学
嵌入式系统
计算机硬件
电子工程
计算机体系结构
工程类
古生物学
生物
航空航天工程
作者
F. Garzetti,N. Lusardi,N. Corna,Gabriele Fiumicelli,F. Cattaneo,Gabriele Bonanno,A. Costa,E. Ronconi,A. Geraci
出处
期刊:Electronics
[MDPI AG]
日期:2024-12-06
卷期号:13 (23): 4825-4825
标识
DOI:10.3390/electronics13234825
摘要
Over the last ten years, the need for high-resolution time-domain digital signal production has grown exponentially. More than ever, applications call for a digital-to-time converter (DTC) that is extremely accurate and precise. Skew compensation and camera shutter operation represent just a few examples of such applications. The advantages of adopting a flexible and rapid time-to-market strategy focused on fast prototyping using programmable logic devices—such as field-programmable gate arrays (FPGAs) and system-on-chip (SoC)—have become increasingly evident. These benefits outweigh those of performance-focused yet expensive application-specific integrated circuits (ASICs). Despite the availability of various architectures, the high non-recurring engineering (NRE) costs make them unsuitable for low-volume production, especially in research or prototyping environments. To address this trend, we introduce an innovative DTC IP-Core with a resolution, also known as least significant bit (LSB), of 52 ps, compatible with all Xilinx 7-Series FPGAs and SoCs. Measurements have been performed on a low-end Artix-7 XC7A100TFTG256-2, guaranteeing a jitter lower than 50 ps r.m.s. and offering a high dynamic range up to 56 ms. With resource utilization below 1% and a dynamic power dissipation of 285 mW for our target FPGA, the design maintains excellent differential and integral nonlinearity errors (DNL/INL) of 1.19 LSB and 1.56 LSB, respectively.
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