Multilevel interconnections for ULSI and GSI era

A high performance interconnection network on a chip is essential to match the ever improving performance of the semiconductor devices they interconnect. This issue reviews the need, some fundamental background justifying the need, approaches one can take in trying to satisfy the need, and associated issues related to the concept of multilevel interconnection (MLI) technology for the ULSI/GSI era of the silicon integrated circuits, with emphasis on materials and the processes that will lead to an acceptable MLI scheme. Thus besides discussing the MLI concepts and implementation issues, properties of metals and their alloys (especially those of Cu and Al), diffusion barrier/adhesion promoter, interlayer dielectrics, deposition and etching of mateials, planarization issues, reliability issues, and new materials concepts are presented. Emphasis is obviously placed on the presently focused research on replacing aluminum with copper based interconnections. The author's viewpoint on gradual changes in replacing current materials with newer mateials as they become available is also presented. A synergism between the materials sets for on-chip and off-chip interconnections has been pointed out.